Help needed... regarding debugging of the testbench for uart

[sharada.144]

Hi. This is Sharada. I am working on uart. I am getting the following errors while executing the uart testbench on ncsim. I am attaching the related files in this post. Anybody please help me ASAP.

Thanks and regards,
Sharada.V

The related files are located in the following link:



The errors occuring are:

ncvhdl -mess uart_finaltb.vhd
ncvhdl: 06.11-s004: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
uart_finaltb.vhd:
wait for 120 ns;
|
ncvhdl_p: *E,EXPEND (uart_finaltb.vhd,54|19): expecting the reserved word 'END' [9.2].
R_W <= '1';
|
ncvhdl_p: *E,EXPEND (uart_finaltb.vhd,61|14): expecting the reserved word 'END' [1.2].
wait for 100 ns;
|
ncvhdl_p: *E,ARCNMM (uart_finaltb.vhd,62|14): architecture body identifier mismatch (TEST1/NS) [1.2].
DBUS <= "01101001";
|
ncvhdl_p: *E,EXPACE (uart_finaltb.vhd,64|0): expecting a library unit [11.1].
end test1;
ncvhdl_p: *E,UXPEOF (uart_finaltb.vhd,75): unexpected end of file.
errors: 5, warnings: 0
Job ended with error status: 1