help needed in Verilog-AMS simulation using ADE (trying from past 15 to 20 days)

[something11]

Hi all
i have written verilog-AMS code for adc and symbol for this is automatically generated. i used this symbol and created schematic of testbench when i try to simulate this i am getting an error that I0:is an an instance of undefined model adc.but i have already written the verilog-ams code for ADC and i am using that symbol only.
plzzzzzz help me to solve this issue

 

[erikl]

How did you attach the symbol to your code? VAMS code filename? symbol view name?

 

[something11]

symbol view only

 

[erikl]

symbol view only

How did you tell the symbol view which VAMS code filename should it connect to?

 

[something11]

i have given model name as adc_2 and same created as symbol

 

[erikl]

i have given model name as adc_2 and same created as symbol

Copy your symbol view to a veriloga view. Your VAMS model adc_2 should be in a file with the name veriloga.va . Put this file into your veriloga view. See this directory structure:

 

[something11]

i have checked it it is already there with the name as verilog.vams