Well, your offset voltage is going to be mainly from mismatch in your preamplifier. It depends on layout, size of the devices on your amplifier and process. You didn't say what process you are using, but as an example, for CMOS process, Vt offset is usually in the form of (Vmismatch/sqrt(W*L)), where W & L is width and lenght of your transistor and Vmismatch is a process dependent value. You size up your transistor until you meet your mismatch target or you can calibrate the offset voltage out as your suggest. Another popular way to lower offset is to chop the input, but this limits your speed.
You can simulate with offset by putting a voltage source with the expected offset value in series with the input on one of the input or use monte-carlo simulation.