If any of you know any good materials on SDC's DRC like set_max_capacitance, set_max_fanout etc. kindly share with me. My primary doubt is that: I can understand that the set_max_capacitance is related to specifying the maximum capacitance value each node can have in the chip but i dont know how setting this value in SDC is related with the original capacitance value in the lay-out.
When the tool is optimizing lauout (route optimization), it tries to minimize the total net capacitance of the net in the following ways:
- insert additional buffers (split long wires or lower number of loads)
- re-route wires to minimize their length
- move cells close to each other
Usually, this attr (max_cap) as well as max_tran attr have higher priority than timing.
Hi thanks for your reply. But i would like to know how these values are actually choosen in chip design. For ex: if i want to make one processor chip, how do i know what should be the max_cap/max_tran value.
In general case, these values comes with libraries, that you are using (the cells of these libraries were characterized in output_pin_load/input_pin_transition range). So, in order to be in the characterization range, you should limit each net capacitance and transition. You must not exceed characterization range!!!
You may set the max_cap lesser than in your libraries - as result, the design will be bigger (more buffers, or bigger cells), but the noise immunity (for example) is better. You may imagine some other design parameters that will be changed.
Still, the question is - which value (must be equal or less than those in libraries) may you set for the design - no common rule . It is up to you, up to the main goal of your design. Try the different values, see the results (area, timing, power ...) and choose the most appropriate for you. This is my understanding.