VHDL/verilog are HDL language though those can be used for verification also.
But it think HVL like specman, vera, system verilog are good but system verilog is becoming more popular as verification langauge.
For system verilog u will a lot of material on internet.
HVL (Hardware verification language) are useful for designing the testbench components and checkers. HDl lacks the advanced level of randomization/temporal checkers/coverage features which are backbone of any verification environment.