JVNPAVANKUMAR
Junior Member level 2
HI i need to know about verificatio for my final thesis
which of these languages are best for verification ?
1)VHDL 2)VERILOG 3)System Verilog
If system verilog is the one, are there any good free tools(in terms of optimisation ) for implementing System verilog?
can any one suggest me some good books for DFT and VERIFICATION using VHDL/System Verilog?
which of these languages are best for verification ?
1)VHDL 2)VERILOG 3)System Verilog
If system verilog is the one, are there any good free tools(in terms of optimisation ) for implementing System verilog?
can any one suggest me some good books for DFT and VERIFICATION using VHDL/System Verilog?