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HELP needed for learning verificatoin

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JVNPAVANKUMAR

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HI i need to know about verificatio for my final thesis

which of these languages are best for verification ?
1)VHDL 2)VERILOG 3)System Verilog

If system verilog is the one, are there any good free tools(in terms of optimisation ) for implementing System verilog?

can any one suggest me some good books for DFT and VERIFICATION using VHDL/System Verilog?
 

pintuinvlsi

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VHDL/verilog are HDL language though those can be used for verification also.
But it think HVL like specman, vera, system verilog are good but system verilog is becoming more popular as verification langauge.
For system verilog u will a lot of material on internet.
 

alok_msh

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HVL (Hardware verification language) are useful for designing the testbench components and checkers. HDl lacks the advanced level of randomization/temporal checkers/coverage features which are backbone of any verification environment.
 

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