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Help needed for basic opamp design

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cheenu2002 said:
Hi,
I have a basic question. How to indentify the positive and negative terminals for opamp?
Like in my case, I want to find the + & -ve terminals for the single stage pmos input diff pair.

you could identify the direction of the current variations induced by the variations of the small signal voltage applied to the input terminal as they flow in the output resistance of the first stage (in a Norton-like representation).

In your design, for example, the small signal current of QP2 is pushed in the output resistance, so if it increases the voltage rises up! The small signal current of QP1 flows across the mirror and is pulled from the output resistace. An increase of that current causes the output voltage to go down! So, an increase of Vinp causes the current flowing through QP1 to decrease, and the rising of the output voltage as a consequence. The same, if you think to connect +Vd/2 to Vinn, an increase of Vd causes the output voltage to decrease.
But you have another gain stage (common source) that causes another sign inversion. So i think that Inn becomes the non-inverting input.

You could also take into account the sign inversions of the signal. Let's consider the signal applied to Inp. From the gate to the drain of QP1 we have a sign inversion. From the gate to the drain of QN0 we have the second sign inversion. Finally, to reach the output, we have another sign inversion from the gate to the drain of QN2. It appears clear that 3 sign inversions causes Inp to be the inverting input. Inn sees only 2 sign inversions to reach the output that makes it to be the NON-inverting input.

If you consider ONLY the diff pair, Inp remains the non inverting input, and Inn remains the inverting one.

You can always reason this way.

Hope i've been clear, it's my first post.
 

Hi,
Thanks for a clear explanation on how to find the positive and negative terminals for opamp.
So, In the BGR schematic I have attached, IN1 is the inverting input and IN2 is the non-inverting input right?
Then, I think my feedback is wrong.. bcoz I think I should connect the signal in the 2 resistor branch to the inverting input of the opamp and the signal in single resistor branch to noninverting input. Pls correct me if I am wrong.
 

I think so! IN1 results the inverting input: 3 change of sign... i'm quite sure ;D
 

Hi,
I have tried to design a folded cascode. The schematic and AC response are attached with this mail. I have 2 questions:

1. The PhaseMargin is very poor. Can you help me to understand how to
improve PM
2. I am able to easily bias the transistors if I use a pmos current mirror load.
But if I use a current source load, then either qp31,29 or qn14,12 goes into
linear region. I am not able to get how to bias the folded cascode with the
current source load. Is there any technique that I should follow. Can anyone
pls help me.
 

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