Help needed for basic opamp design

[cheenu2002]

Hi,
I am starting to learn analog IC design with opamp design. I am trying out with a pmos input pair diffamp. The schematic and AC responses are attached with this mail.
My target specs are :
Supply - 1.8 V
Gain - 60 dB
SR - 5 V/us
Load cap - 1 pF
GBW - 5 MHz
Process - 45nm (Cant use L greater than 0.2um)
Vtn - 0.3V ; Vtp - 0.4 V
Kn - 210e-6 ; Kp - 150e-6 where K = UCox
I tried to design with the procedure given in Allen and Hollberg book, but I am getting very absurd device sizes. So, I have just chosen a current of 50uA and made a start. Initally I tried to place all transistors in saturation and then checked the gain and phase. The responses look poor
Need some help to tweak my design. I dont know how experienced designers go about designing opamps. Can anyone help me. Also, one of my basic questions is why the current mirror is not exactly mirroring the current though W/L is same for both the transistors. I couldnt get which parameter is affecting it.
Also, I dont know if this is the correct way to give input and check the specs. I used a 'vdc' source as input with DC = 800mV, AC magnitude = 0.5 and phase of 0 and 180 degrees. Is it correct?

 

[ankitgarg0312]

for current mirrors check
1. W/L ratios
2. current mirror mosfets are in saturation
3. VDS across device, i suspect this is culprit for different currents as channel length modulation effect will be prominant in low geometry

 

[varunmjman]

Can u change the x axis to logarithamic. I cant make out the frequency response from this picture...

Can u also show the circuit u designed. The mirror wont give the same current if the voltage available in the output section of the mirror is not enough to keep it in saturation

 

[ankitgarg0312]

Can u change the x axis to logarithamic. I cant make out the frequency response from this picture...

Can u also show the circuit u designed. The mirror wont give the same current if the voltage available in the output section of the mirror is not enough to keep it in saturation

dc gain looks good for a single stage amplifer
increase frequency range to see bandwidth , phase margin , gain margin

 

[cheenu2002]

Hi,
As you told, the Vds is different for the current mirror transistors. I dont know how to adjust them. Can you give some inputs for it.
And, I have attached the AC response with log plot. The schematic is also attached with this mail. You can have a look at the schematic for the W/L ratios and the operating point voltages. Can you tell me how to match this design with hand calculations.

 

[ankitgarg0312]

for vds matching:
u can match them but only at one input voltage and one corner , for a common mode voltage range u will not be able to do so, as vds of mirror depends of vgs of pmos input pair.

increase range of frequency for ac analysis to 100mhz or more to see complete freq response.
in diagram only 100khz is visible..

this circuit will not be stable due to missing miller caps, better to try a single stage for basic understanding then attach second stage for futher gain increase

Added after 7 minutes:

i can't say why are ur hand calculations not giving same results as simulations are giving...
one reason can be that hand equations dont have 2nd order effects while 45nm will have a lot of such effects , but this should not bring a drastic change in manual vs simulations results ...

 

[cheenu2002]

Hi,
I did a freq. sweep upto 4 GHz and got the response attached. I see an UGB of 3 GHz and phase -370. How do I get the actual phase margin?

 

[varunmjman]

In the picture of the diff amp u send why all the transistors are of the same size. It wont come like that in the design. Recheck ur design.

Run the simulation for a long frequency range.

Add a miller compensation capacitor.

It will be also really good if u give the inputs to the diffamp using a balun circuit. Its a simple transformer circuit. U can get the pictures from the net.

 

[cheenu2002]

The transistors are not of same size. The multiplier value 'm' is different.
The UGB after adding the miller cap of 300f F is 100MHz and phase is -290 degrees. So, is PM=70 degrees? ( 360 - 290 = 70)
Can you comment on some methods normally used to increase the opamp gain.

 

[wpchan05]

you did not put a load on your output!

 

[varunmjman]

Sorry my mistake...I didnt notice the value of m

In your design you can increase the gain by increasing the gain of the second stage.

Otherwise try using other configurations of opamp which gives higher gain

 

[ankitgarg0312]

what are gain values at 1st stage o/p and 2nd stage o/p??

 

[cheenu2002]

Hi,
I could get a gain of 63dB and PM=30.
I actually wanted to used this opamp in BGR. So, I tried the basic BGR topology but I am not able to force same value to both the inputs of opamp. The current mirror load transistor is going out of saturation. I am not sure if the feedback method I am using is correct.
Can anyone check my schematic and tell me where I am making mistake...
How is the opamp output normally fedback.. I coudnt get any paper which gives that schematic. Almost all of them give only the block diagram where the opamp output is directly connected to the resistors R1, R2 but I dont know how it is done practically.

 

[ankitgarg0312]

you have used a resitor in bjt<4:0> branch,i haven't seen any resitor there, any reason for this?

feedback looks to be wrong , it seems you are giving positive feedback instead of negative feedback.
reverse connection of in1 and in2 .
i hope ur opamp input will stabilize...

while generating vref u should have a bjt + pmos for making it equation
vbe + kr1/r2
u have a resitors there instead of bjt .

 

[cheenu2002]

I think you are asking why there is no BJT in the path from which I am taking 'Vref' output....
I referred to ckt in Allen & Hollberg book and tried to use it. Is it wrong?
The reference is ckt is attached with this mail.
You are right. After interchaning the opamp inputs, its working fine. Can you help me to get the reference output?

 

[ankitgarg0312]

in this ckt r3 and r4 are representing current sources, u already have them using mosftes...

i would suggest to see rajavi for circuit, or i think even google may help u
this circuit is not complete...

yes for bgr refernce node u should have a mosfet,bjt and a resitors...

Added after 2 minutes:

this circuit is very basic and used for generating ptat current

 

[cheenu2002]

Thanks a lot. After using the bgr+res combination at ouput, I am able to get the reference output. Pls refer to attached ckt. Hope its correct
I did a DC sweep of temperature but curve doesnt look like the normal one. Where am I going wrong?

 

[ankitgarg0312]

topology wise circuit looks ok ..
curve will never look like normal one across pvt...

u need to tweak r1/r2 in such a way that this curve getts right shape...

from graph u can see increse in temp increase output that means ptat component increases in a greater extent compared to ctat componenet,,
decrease values of r2 ( in refernce node ) and u will see this curve will start moving in right direction..

but some weird values of r2 like 8.11*R1 will create problem in layouts matching...
so do some tweaking with resitance in reference node while keeping in mind the layout matching ..

congrats for getting bgr done

Added after 1 minutes:

ofcourse u have just met only dc specs yet , transient,ac,noise,psrr etc .. are far away ..

 

[cheenu2002]

Hi,
Thanks for your help. Whatever way I adjust the resistors, I am getting only an inverted bell shaped curve, just the opposite of the normal ones which I see in the books. Is there any problem in my toplology due to which I am getting such a curve?

 

[cheenu2002]

Hi,
I have a basic question. How to indentify the positive and negative terminals for opamp?
Like in my case, I want to find the + & -ve terminals for the single stage pmos input diff pair.