Generally, transistor cap can be caculate by your method, Ctot=Cox*W*L, and they can be influenced by the channel length and Width modulate coeffient, maybe you don't need consider this, because the W and L will be large enough. At the same time, use the transistor cap need note the C-V curve of of the transistor, that is the transistor need to working in satuation region to ensure the cap is acurrate just as your caculate, and the more detail Cox you can build a simple simulation to get it, eg, a RC etal.
Best regards
Hi
when I plot C_Vgs there is an abrupt change when Vgs >0 it is not smooth as your picture. So I don't understand what happen, I think it have to like your picture. Is there any error in my simulation or there is any error in Bsim model. I see some document say that Bsim3 don't describe accurately.
Can anyone give me some ideas about this?
Thank you very much.