akira12345
Newbie level 2
Hi everyone,
I doing a mini project for SOC. I am designing a vechicle speed controller using Verilog and synthesis using Leonardo Spectrum. Then, the schematic is generated to layout by using Design Architect.
During my progress in ic station, i create a new cell for the layout and using schematic sdl file. Then i use auto floorplan and place standard cell and port, and autoroute.
But, after i clean the DRC, LVS states error for missing output port. I couldnt find the missing output port in the layout. Is the process, miss out any instance during auto floorplan, and placing standard cell? How do add the missing port to the layout?
I got an info but need clarification for it. The info states that, when clicking placing standard cell button, ic station may miss out some instances, therefore under logictab, we need to open all sheet of shcematic and select all and click paste instance button in order to build a complete instance and cell inside the floorplan, is it true? if is, why ic station can miss out some instances during placing stdcell? (suppose all cell is build inside a single netlist)
Is there anyway to verify the layout (before DRC clean), to ensure my layout consist all the design instance and port before proceed with DRC?
Thanks for your help.
I doing a mini project for SOC. I am designing a vechicle speed controller using Verilog and synthesis using Leonardo Spectrum. Then, the schematic is generated to layout by using Design Architect.
During my progress in ic station, i create a new cell for the layout and using schematic sdl file. Then i use auto floorplan and place standard cell and port, and autoroute.
But, after i clean the DRC, LVS states error for missing output port. I couldnt find the missing output port in the layout. Is the process, miss out any instance during auto floorplan, and placing standard cell? How do add the missing port to the layout?
I got an info but need clarification for it. The info states that, when clicking placing standard cell button, ic station may miss out some instances, therefore under logictab, we need to open all sheet of shcematic and select all and click paste instance button in order to build a complete instance and cell inside the floorplan, is it true? if is, why ic station can miss out some instances during placing stdcell? (suppose all cell is build inside a single netlist)
Is there anyway to verify the layout (before DRC clean), to ensure my layout consist all the design instance and port before proceed with DRC?
Thanks for your help.
