Re: HELP in 1:4 Demux !!
library ieee;
use ieee.std_logic_1164.all;
entity dmux_1to4_1 is
port(a:in std_logic;
sel :in std_logic_vector(1 downto 0);
b
ut std_logic_vector(3 downto 0));
end dmux_1to4_1;
architecture arch_1to4_1 of dmux_1to4_1 is
begin
b(0)<= a when sel<="00" else
b(1)<= a when sel<="01" else
b(2)<= a when sel<="10" else
b(3)<= a when sel<="11" else
;
end arch_1to4_1;
Added after 3 minutes:
library ieee;
use ieee.std_logic_1164.all;
entity demux_2to4_3 is
port(sel: in std_logic_vector (1 downto 0);
a :in std_logic;
b: out std_logic_vector(3 downto 0));
end en_2to4_decoder3;
architecture arch_2to4_decoder3 is
begin
process(sel)
begin
if sel<="00" then b<=a;
elsif sel<="01" then b<=a;
elsif sel<="10" then b<=a;
elsif sel<="11" then b<=a;
end if;
end process;
end arch_2to4_3;
Added after 6 minutes:
library ieee;
use ieee.std_logic_1164.all;
entity demux_1to4_4 is
port(sel: in std_logic_vector (1 downto 0);
a :in std_logic;
b: out std_logic_vector (3 downto 0));
end demux_1to4_4;
architecture arch_1to4_4 of demux_1to4_4 is
begin
process(sel)
begin
case sel is
when "00" =>
b(0)<=a;
when "01" =>
b(1)<=a;
when "10" =>
b(2)<=a;
when "11" =>
b(3)<=a;
end case;
end process;
end arch_1to4_4;