Help me write a simple 1:4 Demux !!

[cloudz88]

Anybody know how to write a 1:4 Demux?

i juz need a simple sample of a 1:4 Demux coding so that i can take it as a reference to do my assignment....

plz help...thanks lots!!

 

[gck]

how to demux code in verilog

entity demux is
port( input: in std_logic;
sel : in std_logic_vector(1 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;

architecture demux_arc of demux is
begin

output(0) <= input and (not sel(0)) and (not sel(1));
output(1) <= input and sel(0) and (not sel(1));
output(2) <= input and (not sel(0)) and sel(1);
output(3) <= input and sel(0) and sel(1);

end demux_arc;


You can search in any book, they definatly has the code

 

[swapnil_vlsi]

Re: HELP in 1:4 Demux !!

library ieee;
use ieee.std_logic_1164.all;

entity dmux_1to4_1 is
port(a:in std_logic;
sel :in std_logic_vector(1 downto 0);
but std_logic_vector(3 downto 0));
end dmux_1to4_1;

architecture arch_1to4_1 of dmux_1to4_1 is
begin
b(0)<= a when sel<="00" else
b(1)<= a when sel<="01" else
b(2)<= a when sel<="10" else
b(3)<= a when sel<="11" else
;
end arch_1to4_1;

Added after 3 minutes:

library ieee;
use ieee.std_logic_1164.all;

entity demux_2to4_3 is
port(sel: in std_logic_vector (1 downto 0);
a :in std_logic;
b: out std_logic_vector(3 downto 0));
end en_2to4_decoder3;

architecture arch_2to4_decoder3 is
begin
process(sel)
begin
if sel<="00" then b<=a;
elsif sel<="01" then b<=a;
elsif sel<="10" then b<=a;
elsif sel<="11" then b<=a;
end if;
end process;
end arch_2to4_3;

Added after 6 minutes:




library ieee;
use ieee.std_logic_1164.all;

entity demux_1to4_4 is
port(sel: in std_logic_vector (1 downto 0);
a :in std_logic;
b: out std_logic_vector (3 downto 0));
end demux_1to4_4;

architecture arch_1to4_4 of demux_1to4_4 is
begin
process(sel)
begin
case sel is
when "00" =>
b(0)<=a;
when "01" =>
b(1)<=a;
when "10" =>
b(2)<=a;
when "11" =>
b(3)<=a;
end case;
end process;
end arch_1to4_4;

 

[echo47]

HELP in 1:4 Demux !!

Or Verilog:

module demux (in, sel, out);
  input         in;
  input   [1:0] sel;
  output  [3:0] out;

  assign out = in << sel;
endmodule

 

[karnizhu]

Re: HELP in 1:4 Demux !!

Or Verilog:

module demux (in, sel, out);
  input         in;
  input   [1:0] sel;
  output  [3:0] out;

  assign out = in << sel;
endmodule

thank echo47 very much for giving us a such finished demux coding,i have test it by QuestaSim6.2:it's all OK,and i extend it for a demux which can be paramized with the output width, see below:

module demux(
out,
in,
sel
);
parameter W = 4;
parameter L = 2;

output[W-1:0] out; //demux out
input in; //demux input
input[L-1:0] sel; //demux select signal

assign out = in << sel;

endmodule

the testbench is here:

module t_demux();
parameter W8 = 8;
parameter L3 = 3;

reg in;
reg[L3-1:0] sel;
wire[W8-1:0] out;

demux DM(
out,
in,
sel
);
defparam DM.W = W8;
defparam DM.L = L3;

initial begin
in = 1'b1;
sel = 3'b0;
repeat( W8 )
#(10) sel = sel + 1'b1;
$finish;
end
endmodule

thank echo47 again!