Help me write a code for CoreGen memory module

[suddy72]

Hi guys,

I thought i had cracked the core gen memory module but its not doing what i expected.

When you create the module, you have your data_in line , clk , address , write enable and data_out signals.

Do you have to have a command like address <= address + 1 to get to the next memory address or will it do it aumomatically after every rising clock edge?

I have written code so that writes data_in to every addresss in the module then when it gets to end it jumps to the second address down and leaves the first one alone. Then when we = '0' is should show the contents in memory 1 , but it doesnt , it seems like its writing to that location , even though i have not told it to.

any help or code would be great.

cheers people.

 

[rberek]

Re: CoreGen Memory

You have to update the address yourself. It does not do it for you.

Why does it seem like its writing to that location?

 

[suddy72]

Re: CoreGen Memory

Thanks for reply.

See when the address gets to the end of the memory , ie say 1111 does it automatically go back to 0000 or does it just stop ?

 

[rberek]

Re: CoreGen Memory

The address doesn't automatically do anything. You are responsible for providing the address. It will write to the address you provide, and assume nothing else about the address.

 

[suddy72]

Re: CoreGen Memory

So does that mean when the address is at "1111" which is the last address in my memory array, if the command is address ,= address + 1; will it just stay where it is or what will it do ?

 

[rberek]

Re: CoreGen Memory

My assumption:

The value address that you are generating is a register that provides the input to the memory's address port. The register will take on whatever value you give it. If the address register is 4 bits, and it is at 1111 ,when you increment it by one, it will go to 0000. If it is five bits, its value will go to 10000. In your RTL, you have connected that register to the address port to provide the address input. If your memory address port is 4 bits wide, the memory's address value will change to 0000. If it is five bits wide, your memory's address value will change to 10000.

 

[echo47]

CoreGen Memory

If you can show us your code (preferably a short complete module), maybe someone here can help you debug it.

If your are using Xiling XST, remember that you could create the RAM by using an HDL register array instead of instantiating a coregen RAM. You may find it easier to use and debug. For more info, see your XST User Guide chapter "HDL Coding Techniques" section "RAMs and ROMs".