help me with this verilog code...............whenever i compile i get 4 errors plzzzz

[maheshkumar.g]

module alu(out,cy,in1,in2,cin,bi,sel,sel1);
input [4:0] in1,in2;
input [2:0] sel,sel1;
input cin,bi;
output [4:0] out;
output cy;
reg [4:0] out;
reg cy;
always @(in1,in2,sel,sel1,cin,bi)
begin
case(sel)
3'b000: cla ma1(out,cy,in1,in2,cin);
3'b001: bls ma2(out,cy,in1,in2,bi);
3'b010: bm ma3(out,cy,in1,in2);
3'b011: lu ma4(out,sel1,in1,in2);
endcase
end
endmodule

module cla(sum,cy,a,b,cin); 
output cy; 
output [3:0] sum; 
input [3:0] a,b; 
input cin; 
reg[3:0] g,p,co; 
reg [3:0] sum;  
always @(a,b,cin)
begin
sum=a^b^cin;
g[3:0]=a[3:0] & b[3:0]; 
p[3:0]=a[3:0] ^ b[3:0]; 
co[0]=g[0]|(p[0]&cin);
co[1]=g[1]|(p[1]&co[0]);
co[2]=g[2]|(p[2]&co[1]);
co[3]=g[3]|(p[3]&co[2]);
cy=co[3];
end
endmodule 


module bm(temp,cy,in1,in2);
input in1,in2;
output temp,cy;
wire [4:0]in1;
wire [4:0]in2;
reg [9:0] temp;
reg [1:0] sel;
reg cy;
integer i;
reg plsb;
always @(in1,in2)
begin
plsb=1'b0;
temp={{5'b00000},{in1[4:0]}};
for(i=0;i<5;i=i+1)
begin
sel={temp[0],plsb};
case(sel)
2'b00:begin
plsb=temp[0];
temp={temp[0],temp[9:1]};
end
2'b01:begin
temp[9:5]=temp[9:5]+in2[4:0];
plsb=temp[0];
temp={temp[0],temp[9:1]};
end
2'b10:begin
temp[9:5]=temp[9:5]-in2[4:0];
plsb=temp[0];
temp={temp[0],temp[9:1]};
end
2'b11:begin
plsb=temp[0];
temp={temp[0],temp[9:1]};
end
endcase
end
cy=temp[9]|temp[8]|temp[7]|temp[6]|temp[5];
end
endmodule


module bls(d,br,a,b,bi);
input [3:0] a,b;
output [3:0] d,br;
input bi;
reg [3:0] d,br,g,p;
always @(a,b,bi)
begin
d<=(a[3:0]&~b[3:0]&~bi)|(~a[3:0]&b[3:0]&~bi)|(~a[3:0]&~b[3:0]&bi)|(a[3:0]&b[3:0]&bi);
g[3:0]=~a[3:0]&b[3:0];
p[3:0]=(~a[3:0]|b[3:0])&bi;
br[0]=g[0]|(p[0]&bi);
br[1]=g[1]|(p[1]&b[0]);
br[2]=g[2]|(p[2]&b[1]);
br[3]=g[3]|(p[3]&b[2]);
end
endmodule


module lu (y,oper,a,b);
input [3:0]a;
input [3:0]b;
input [3:0]oper;
output[3:0] y;
reg [3:0]y;
always@(a or b or oper)
begin
case(oper)
4'b0000:y=a|~b;
4'b0001:y=a|~(a&b);
4'b0010:y=(a|(~b|a));
4'b0011:y=(a|b)-1;
4'b0100:y=~a;
4'b0101:y=~(a|b);
4'b0110:y=(a&(~b));
4'b0111:y=~(a&b);
4'b1000:y=(&a);
4'b1001:y=~(|b);
4'b1010:y=a<<3;
4'b1011:y=b>>3;
endcase
end
endmodule

 

[rca]

which king of error did you have? could you share to help?

 

[FvM]

It's actually only one error. You can't instantiate modules in a sequential block. Review your favourite Verilog text book for details.

always @(in1,in2,sel,sel1,cin,bi)
begin
case(sel)
3'b000: cla ma1(out,cy,in1,in2,cin);
3'b001: bls ma2(out,cy,in1,in2,bi);
3'b010: bm ma3(out,cy,in1,in2);
3'b011: lu ma4(out,sel1,in1,in2);
endcase
end

 

[maheshkumar.g]

thank you for u r suggestion fvm i come back to u if i have any problems again............