I have several clock in my design. They have different frequency. I have to set false path from clock to clock. The netlist pass the STA chencking, However, it failed in dynamic simulation. How could i solve this problem in my STA scripts?
Only if the clocks are unrelated to each other, then setting false path from clock to clock is ok. If it passes STA, you should not have any errors in dynamic simulation. Unless, the clocks are not exactly unrelated with each other or something wrong with your stimulus.
dynamic sim can not handel cross clock domain , You will see some case propagate the unknow(x) signal in flip-flop with feedback mux with wrong behavior . As the pre-post said . comment out those cross domain timing check . I do it by hand to modify sdf file . Another issue is the test pattern could be shift one clock in testing real chip . You should tell the testing engineer to accept part as good die when it happened .