avt
Member level 5
I'm designing a CMOS TX driver. It has anupper and a lower biasing current source. By controling the current sources the common mode voltage is regulated as described in the Boni paper.
Now I figured out that there is a seriuous problem with the stacked 4 nmos-switches which "guide" the current. Because the two upper nmos are running as source followers (and I have no triple well process) I have problems with the bodyeffect of the devices. Over process variations the influence of bodyeffects varies so much, that I get huge overswinging and quite big assymetries between rise and fall times of the differential signals - and in this way differential skew.
I thought about using pmos devices - but in a 0.35um process there is not enough headroom voltage if you have 0.7v vth and a decent vdsat of 300mV (which already makes the mosfet quite huge.
So I think it might be a good idea to use nmos as the lower devices and pmos as the upper devices. This means more or less to have on the lower have a nmos diffpair and a pmos in the upper half. This solves at least the problem of bodyeffect. Anyway still have problems to get symmetric rise and falltimes - my sizing for the devices is right now to have the same vdsat or alternatively vgsteff on all devices (when driven by the common mode voltage). But it seems to me that due to parasitic capacitances rise and fall times still remain somehow assymetric - especialy when I drive the devices out of saturation deeper into subtreshold and the linear region by increasing the differential input voltage.
Furtheron I have figured out that there is also a dependence on the input common-mode-voltage - I owuld have assumed to hav nearly no dependence on input cm-voltage as long as the mosfets of the upper and lower current sources remain in saturation (which is the case) ...
If some of the guys here who have also designed either a switching circuit like in the boni-paper or with the pmos/nmos-configuration have some good advice, I would be very happy to hear about it. If you guys like to share your thoughts on a good predriver circuit let me know also ( right now I use two cml buffer as a buffer and level shifter and before that a clocked cmos latch in order to get low-skew data input signals - the problem with this configuration is, that you drive the first of the two cml buffers deeply into linear or subtreshold/off region - what results in some skew/spiking)
Now I figured out that there is a seriuous problem with the stacked 4 nmos-switches which "guide" the current. Because the two upper nmos are running as source followers (and I have no triple well process) I have problems with the bodyeffect of the devices. Over process variations the influence of bodyeffects varies so much, that I get huge overswinging and quite big assymetries between rise and fall times of the differential signals - and in this way differential skew.
I thought about using pmos devices - but in a 0.35um process there is not enough headroom voltage if you have 0.7v vth and a decent vdsat of 300mV (which already makes the mosfet quite huge.
So I think it might be a good idea to use nmos as the lower devices and pmos as the upper devices. This means more or less to have on the lower have a nmos diffpair and a pmos in the upper half. This solves at least the problem of bodyeffect. Anyway still have problems to get symmetric rise and falltimes - my sizing for the devices is right now to have the same vdsat or alternatively vgsteff on all devices (when driven by the common mode voltage). But it seems to me that due to parasitic capacitances rise and fall times still remain somehow assymetric - especialy when I drive the devices out of saturation deeper into subtreshold and the linear region by increasing the differential input voltage.
Furtheron I have figured out that there is also a dependence on the input common-mode-voltage - I owuld have assumed to hav nearly no dependence on input cm-voltage as long as the mosfets of the upper and lower current sources remain in saturation (which is the case) ...
If some of the guys here who have also designed either a switching circuit like in the boni-paper or with the pmos/nmos-configuration have some good advice, I would be very happy to hear about it. If you guys like to share your thoughts on a good predriver circuit let me know also ( right now I use two cml buffer as a buffer and level shifter and before that a clocked cmos latch in order to get low-skew data input signals - the problem with this configuration is, that you drive the first of the two cml buffers deeply into linear or subtreshold/off region - what results in some skew/spiking)
