[SOLVED] Help me with logic gates in a code for 4-bit counter

[karthiga05]

Hi guys. I've posted a few threads before regarding counters. This is still regarding a counter. my 4-bit counter. But im not sure if the part in RED is right.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal ain,s,c:std_logic_vector(3 downto 0) :="0000";
signal bin:std_logic_vector(3 downto 0):="0001";

--configuration specification
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);

begin

u1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(0));
u3:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(1));
u4:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(2));

counterrocess(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
ain <= c or ain;
s <= ain or bin;
c <= s and c;

end if;
end process;

count <= s;

end behav_counter4;

---------- Post added at 14:34 ---------- Previous post was at 14:30 ----------

it doesnt loop.

 

[Iamventure]

Hi,
I am sorry to ask this. But why is there an adder for designing a counter?
I hope this would be it for the counter logic.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

begin

signal count_sig : std_logic_vector (4 downto 0);

counter : process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
count_sig <= (others => '0');
elsif clk'event and (clk='1') then
count_sig <= count_sig + 1;
end if;
end process;

count <= count_sig;

end behav_counter4;

 

[karthiga05]

its because im required to use this method. if im not, of course i would use the simpler one.

 

[FvM]

But im not sure if the part in RED is right.

I think, it's wrong in two regards:
- it's not represneting an adder
- it creates a syntax error in the present design, because the signal s has multiple drivers.

Using an adder to build a counter is basically correct, also the behaviotal description count_sig <= count_sig + 1; simply infers an adder. In so far, you can expect that all (correct) counter implementations end up in the same gate level netlist.

 

[sanju_]

replacing
"s <= (others => '0');" line to "count <= (others => '0');" can over come that error(multiple drivers)
https://www.edaboard.com/threads/216962/ -----> this is the recent post of same person