Re: Help FPGA holdtime
THe hdl code is long, i cant post it in here.
From the timing report, the destination clock is regwr_clk.
From the hdl code, regwr_clk has a mux to select between Test clk and XIN.
Code:
wire regwr_clk = TEST ? XIN : TEST_CLK;
whereas the XTAL_OUT is connected to XIN.
For the timing constraints, I only set one timing constraint, others are just pin assignment constraints.
Code:
NET "XIN" TNM_NET = "XIN";
TIMESPEC "TS_XIN" = PERIOD "XIN" 31.25 ns HIGH 50 %;
When i do my synthesis, implementation, i got hold time violation on that which i'm not sure
(i)
why and
(ii)
how to overcome it. And also how to determine the
(iii)Requirement: 0.000ns
(iv)Positive Clock Path Skew: 7.879ns
Plz help, thanks.