Re: some LDO questions
jwfan said:
The Pmos is a CS amplifier if it is in saturation region.
how to assure the PMOS is in saturation region. I should set opamp output to ranges which fully off and on the pass device, right?
jwfan said:
The DC gain of the OpAmp is determined by you loop stability and the output accuracy.
yes, i've noticed it. but how far should i go with opamp's gain to ensure low quiescent current work. it's the main tradeoff. i need rough values. i'm modelling it and then i'll have to design low voltage opamp with this gain.
Added after 29 minutes:
v_c said:
Are you looking at the article "Stability Analysis of low-dropout linear regualators with a PMOS pass element" by E. Rogers?
yes, that's this article
\[G_{pmos} = g_m R_{o,pmos}\]
i've looked to output file and have gm=35.35m and Rout(at the output of LDO) only 0.5ohm - i've got it from .tf analysis am i right??
You wrote Ro,pmos so is that 1/gds?? if yes gds is equal to 1.92, W/L is 10k
what's wrong, maybe my model is not correct. Did you hear about any applications modelling it?
v_c said:
I think you can use the transconductance in a spice model.
so i should use constant gm value instead of real PMOS during the simulation?
if yes so what value. i thought to model gm during saturation region to change with current
v_c said:
Also note that in this paper he assumes that the output load resistance is high -- high enough to be neglected from the expressions from the poles and zeros that are calculated.
why neglected?? if it's high, the pole layis in low frequency (see example in this paper fp3=2.65k)
i don't understand also one thing. I think the bypass capacity is not necessary, and i would consider only two low freq poles and one zero.
but if i use buffer at the opamp's output its output impedance will be low, and will create high frequency pole.
so it will last only one low frequency pole and the zero won't be essential
correct me if i'm wrong, please
regards
Luke