please help me for biasing of all npn push pooll stage
This mean's that all of transistors must be npn.
Also output stage maked with power transistors (with low beta)
In attachment there is a very classic schematics of NPN output stage with
thermal coupled biasing. Q1, Q3 and Q5 should be mounted on the same heatsink.
The resistors values depend on the power and transistors used.
Whis R1 you trim the output stage biasing current trading between minimal current and minimal signal distorsion.