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Help me understand hold time and hold time violation

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vcnvcc

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Understanding Hold time

I know setup time violation, but could you tell me abt hold time, and hold time violation. I know the defination, But actually in real environment what the things are?
Please give a simple example to understand.

Regards.
 

neo_chip

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Re: Understanding Hold time

*****************************flop1
*****************************|D Q|--[logic]--+
*************+-----------+-------+--|>> |********|** flop2
*************|**clk1b*********************+--|D Q|
****X-------------+--|>o--+------------------------------------|>> |

Hold Slack = Arrival time - required time.

If the delay in the clock path to flop2(clk1b) is more, then the required time is increased, thus causing a negative slack (i.e.) hold violation. In general if the data changes in the hold window, hold violation occurs. In this case due to the delay in the clk path, the clock edge to the flop2 to is delayed. So the data changes in the hold window, thus causing a hold violation.
 

spauls

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Re: Understanding Hold time

When hold fail, the chip does not work in any frequency (even 1hz).
 

asping

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Understanding Hold time

Hold time violation is the serious problem for a chip design. the clk time ended before the data ended , this is hold violation.
If there are setup violation, the chip maybe be operate at low frequency, but hold violation,the chip will not work at any frequency.
 

steven852

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Re: Understanding Hold time

Another view of hold time violation is like this:

If a clock rising edge launches a data to the next clock rising edge, let's call the first rising edge launching edge and the second rising edge capture edge. The data must be stable after the launching edge for a while. During this moment the data cannot be caught the capture edge. Otherwise, the data is lost. However, the hold time doesn't depends on the clock period, ie., the difference between capture and launching edges, interesting, right?
 

rajesh9999

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Re: Understanding Hold time

In an ASIC flow, Set up and hold times conditions exists because of the non-zero finite time it requires for the transmission gates in the flip-flops(look at a transistor circuit of a flip-flop) to completely open or completely close. The opening and closing of the transmission gates occur at clock edges. Therefore the data needs to be stable at these clock edges. Hold time refers to the the time interval it takes for the transmission gate in the flip-flop to completely close.

Hold time condition refer to the requirement that the data captured by a flip-flop should not reach the next flip-flop in the path so fast that the transmission gate of the next flop flop has not closed completely. See Figure. In the figure, the time it takes for d1 to reach flipflop_2 should be greater than the hold time of flipflop_2.

schematic : flipflop_1 ---->(logic)------->Flipflop_2
data at launch edge : d1 ----------->(logic)-------->Flipflop_2

Hold time voilations are flagged by turning to the best case pvt scenario for a library (when the gates are at their fastest speed) and finding the fastest path (ie, path with least delay). The path delay of this path (measured by setting the library to the best case pvt) will give us the lower bound on the earliest arrival of the captured signal(data) to the end point (for example the end point in the above figure is Flipflop_2). If this number is less than the hold time of Flipflop_2 (note - hold times of every flip flop is available in the library), then a hold voilation has occurred.

Hope this helps.
 

funzero

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Re: Understanding Hold time

when we come to setup and hold time , this mean the logic between two DFF should not run too slow(setup) or two fast (hold).
Td-q + Tlogic_delay>=Thold
 

sysco_stevens

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Re: Understanding Hold time

hold time violation is often caused by clock skew.

or too fast data path.

best regards




vcnvcc said:
I know setup time violation, but could you tell me abt hold time, and hold time violation. I know the defination, But actually in real environment what the things are?
Please give a simple example to understand.

Regards.
 

laglead

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Re: Understanding Hold time

when one signal edge run faster than its related clock edge, hold time violation occurs.
 

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