Non AMP

Help me translate VHDL code to Verilog

Thread starter lgeorge123
Start date Dec 12, 2011

Status: Not open for further replies.

Dec 12, 2011

#1

L

lgeorge123

Full Member level 2

Under this VHDL code :
if adcA_int > (trigLevel&"00") AND oldSample <= (trigLevel&"00")

How do i translate this code to verilog ????

Dec 13, 2011

#2

S

shaiko

Advanced Member level 5

Do you understand what it means in VHDL?

Status: Not open for further replies.

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