lgeorge123
Full Member level 2
Under this VHDL code :
if adcA_int > (trigLevel&"00") AND oldSample <= (trigLevel&"00")
How do i translate this code to verilog ????
if adcA_int > (trigLevel&"00") AND oldSample <= (trigLevel&"00")
How do i translate this code to verilog ????