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let me show some sample example you just modify this and go ahead The trend here seems to be to place the intended clock input divided by two into the integer range of variable cnt and the if statement checking the value of cnt. This should work for any input clock value, assuming you change the appropriate values 25.175MHz to 1Hz Clock Divider
entity c1hz is
port( clk:in bit; clkoutut bit);
architecture behavior of c1hz is
variable cnt : integer range 0 to 12587500;
if(clk'event and clk='1') then
cnt := cnt+1;