moonnightingale
Full Member level 6
Hi i have written a code which is working fine in simulation.
When i burn it on my FPGA kit Spartan 3E, i am unable to see the effect due to very high clock.
Its clock is 50 MHz which comes to be 2x10(-8) seconds
I want this clock timing to be 5 seconds which means 0.2 Hz.
How can i do that ?Is some change required in UCF??
Plz Guide me
this is my code
module statediagram(y_out,x_in, clock, reset);
output [1:0] y_out;
input [1:0] x_in;
input clock,reset;
reg [1:0] y_out;
reg [30:0] count;//
reg[1:0] state,next_state;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always@(posedge clock,negedge reset) // The negedge reset event is asynchronous since it matches the
//if(~reset) statement
if (reset==0)state<=S0;
else state<=next_state;
always@(state,x_in) //This always block forms the next state
case(state)
S0:if(x_in==2'b01) next_state=S1;else next_state=S0;
S1:if(x_in==2'b01) next_state=S2;else next_state=S1;
S2:if(x_in==2'b01) next_state=S3;else next_state=S2;
S3:if(x_in==2'b01) next_state=S0;else next_state=S3;
endcase
always@(state,x_in) //This always block forms the output
case(state)
S0: y_out=2'b00;
S1: y_out=2'b01;
S2: y_out=2'b10;
S3: y_out=2'b11;
endcase
endmodule
When i burn it on my FPGA kit Spartan 3E, i am unable to see the effect due to very high clock.
Its clock is 50 MHz which comes to be 2x10(-8) seconds
I want this clock timing to be 5 seconds which means 0.2 Hz.
How can i do that ?Is some change required in UCF??
Plz Guide me
this is my code
module statediagram(y_out,x_in, clock, reset);
output [1:0] y_out;
input [1:0] x_in;
input clock,reset;
reg [1:0] y_out;
reg [30:0] count;//
reg[1:0] state,next_state;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always@(posedge clock,negedge reset) // The negedge reset event is asynchronous since it matches the
//if(~reset) statement
if (reset==0)state<=S0;
else state<=next_state;
always@(state,x_in) //This always block forms the next state
case(state)
S0:if(x_in==2'b01) next_state=S1;else next_state=S0;
S1:if(x_in==2'b01) next_state=S2;else next_state=S1;
S2:if(x_in==2'b01) next_state=S3;else next_state=S2;
S3:if(x_in==2'b01) next_state=S0;else next_state=S3;
endcase
always@(state,x_in) //This always block forms the output
case(state)
S0: y_out=2'b00;
S1: y_out=2'b01;
S2: y_out=2'b10;
S3: y_out=2'b11;
endcase
endmodule