help me to get the output of the following verilog code

[Sreya39]

what is output of following verilog code

Hi
I am getting the output for the first submodule corr1(iecorrouti1,corroutq1)...
i am not able to get the output of remaining submodules... can anyone help me why it is happening and how to correct it.....Thanks

module sreya(clock,Enable,xi1,xq1,corrouti1,corroutq1,corrouti2,corroutq2,corrouti3,corroutq3,corrouti4,corroutq4,corrouti5,corroutq5);
input clock,Enable;
input [4:0] xi1;
input [4:0] xq1;
output [9:0]corrouti1,corroutq1;
output[9:0] corrouti2,corroutq2,corrouti3,corroutq3,corrouti4,corroutq4,corrouti5,corroutq5;
reg [4:0] xi2,xi3,xi4,xi5;
reg [4:0] xq2,xq3,xq4,xq5;
always@(posedge clock) begin
assign xi2 = xi1;
assign xq2 = xq1;
end
always@(posedge clock) begin
assign xi3 = xi2;
assign xq3 = xq2;
end
always@(posedge clock) begin
assign xi4 = xi3;
assign xq4 = xq3;
end
always@(posedge clock) begin
assign xi5 = xi4;
assign xq5 = xq4;
end
corr corr1(.clock(clock),.Enable(Enable),.xi(xi1),.xq(xq1),.yi(corrouti1),.yq(corroutq1));
corr corr2(.clock(clock),.Enable(Enable),.xi(xi2),.xq(xq2),.yi(corrouti2),.yq(corroutq2));
corr corr3(.clock(clock),.Enable(Enable),.xi(xi3),.xq(xq3),.yi(corrouti3),.yq(corroutq3));
corr corr4(.clock(clock),.Enable(Enable),.xi(xi4),.xq(xq4),.yi(corrouti4),.yq(corroutq4));
corr corr5(.clock(clock),.Enable(Enable),.xi(xi5),.xq(xq5),.yi(corrouti5),.yq(corroutq5));
endmodule

 

[echo47]

Difficult to guess what's wrong without seeing 'corr' or the test bench.

In your simulator, try displaying all the signals inside one of the non-working modules. That should show you whatever is causing the problem.

 

[achandra]

Are you looking at the outputs after sufficient number of clocks? If not i guess u won't be getting the outputs because: for each module the inputs need to come after shifting from the registers, so the second module output appears a clock cycle after the first module output and similarly for the rest of the modules too.