A
ahmadagha23
Guest
hi,
I create a ISE8.2 project and add an IP core source (a multiplier) to it, then I add a new vhdl source code as top-level which IP core is instantiated. I synthesized it by synplifypro with two warning that said " IP core is a blakbox" and " timing model for IP core couldn't find". when I implement it I received the following messages in translate step:
ERROR:NgdBuild:76 - File "F:\ise8\myproject\my538\_ngo\mymul.ngo" cannot be
merged into block "m1" (TYPE="mymul") because one or more pins on the block,
including pin "p(7)", were not found in the file. Please make sure that all
pins on the instantiated component match pins in the lower-level design block
(irrespective of case). If there are bussed pins on this block, make sure
that the upper-level and lower-level netlists use the same bus-naming
convention.
Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'm1' with type 'mymul' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'mymul' is not supported in target
'virtex2'.
do you know why?
I refered to xilinx answer database.
regards
I create a ISE8.2 project and add an IP core source (a multiplier) to it, then I add a new vhdl source code as top-level which IP core is instantiated. I synthesized it by synplifypro with two warning that said " IP core is a blakbox" and " timing model for IP core couldn't find". when I implement it I received the following messages in translate step:
ERROR:NgdBuild:76 - File "F:\ise8\myproject\my538\_ngo\mymul.ngo" cannot be
merged into block "m1" (TYPE="mymul") because one or more pins on the block,
including pin "p(7)", were not found in the file. Please make sure that all
pins on the instantiated component match pins in the lower-level design block
(irrespective of case). If there are bussed pins on this block, make sure
that the upper-level and lower-level netlists use the same bus-naming
convention.
Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'm1' with type 'mymul' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'mymul' is not supported in target
'virtex2'.
do you know why?
I refered to xilinx answer database.
regards