Help me sole some problems in an LDO design

[cmosbjt]

Requirement:

0. SiGe 0.18u process.
1. Supply voltage from 3 V to 6 V.
2. Output voltage 2.9 V.
3. Output current 30 mA.
4. Quiescent current less than 1 mA.
5. Load cap 0.1uF, 0201 ceramic cap (assuming no ESR or no good ESR control)
6. Settling time less than 2 uS for all conner, temperature conditions, target at 1 uS.
7. No requirement for PSRR so far.

I got trouble designing this LDO. The load cap is not big enough to put the load pole as dominant pole, but it is also not small enough to put it as the 2nd pole. The 0201 ceramic cap has no control on its ESR, which means no control on the zero for freq compensation. Output 2.9V, but supply voltage range changes from 3 to 6 V, which means the output impedance can be as small as 5 Ohm, or as big as 10k Ohm. The output pole changes dramatically. Quiescent current less than 1 mA, I can not use a supper big buffer to boost the PFET gate pole to very high freq.

Any idea how to design this LDO? Thanks.

 

[hung_wai_ming@hotmail.com]

LDO design help

Difficult. Let me think think and tell you if i can have better method. Your concern is my concern as well. Also, 2us settling is also not easy. 100mV dropout also not easy at VDD=3.0V

 

[cmosbjt]

Re: LDO design help

Difficult. Let me think think and tell you if i can have better method. Your concern is my concern as well. Also, 2us settling is also not easy. 100mV dropout also not easy at VDD=3.0V

Thanks buddy. Let me know if you have solutions.

 

[hung_wai_ming@hotmail.com]

Re: LDO design help

Search for these two guys' paper as they are pretty good in LDO and bandgap reference design.
I believe their papers can help you

 

[melc]

Re: LDO design help

Requirement:

0. SiGe 0.18u process.
1. Supply voltage from 3 V to 6 V.
2. Output voltage 2.9 V.
3. Output current 30 mA.
4. Quiescent current less than 1 mA.
5. Load cap 0.1uF, 0201 ceramic cap (assuming no ESR or no good ESR control)
6. Settling time less than 2 uS for all conner, temperature conditions, target at 1 uS.
7. No requirement for PSRR so far.

I got trouble designing this LDO. The load cap is not big enough to put the load pole as dominant pole, but it is also not small enough to put it as the 2nd pole. The 0201 ceramic cap has no control on its ESR,

I have never seen any good LDO design with filtering caps 0201. I'm just using LDO's not designing them.
There are plenty of LDO's on the market with your requirements, so definitely it's possible.

which means no control on the zero for freq compensation. Output 2.9V, but supply voltage range changes from 3 to 6 V, which means the output impedance can be as small as 5 Ohm, or as big as 10k Ohm. The output pole changes dramatically. Quiescent current less than 1 mA, I can not use a supper big buffer to boost the PFET gate pole to very high freq.

Any idea how to design this LDO? Thanks.

 

[cmosbjt]

Re: LDO design help

Search for these two guys' paper as they are pretty good in LDO and bandgap reference design.
I believe their papers can help you

Thanks. But we prefer a big cap at the output for AC decoupling. 0.1uF is the max number for 0201. I think I need a very precise controlled ESR cap.

 

[scottieman]

Re: LDO design help

How is the chip area requirement?
If it is not tough, I suggest you use a larger power MOS to make the output impedance approach to a ~fixed number that may help you to place the output pole in a well-controlled manner.

Hope it helps
Scottie

 

[hylas]

Re: LDO design help

Since you don't have any specification on DC accuracy (line/load regulation), you may consider to reduce the close-loop gain (reduce gain of error amplifier) to simplify the freq. compensation.

 

[penghan]

Re: LDO design help

Pole-Zero Cancellation technique can meet the requirement.

Refer "A capacitor-free CMOS Low-dropout Regulator With Damping-Factor-Control Frequency Compensation"
Author : Ka Nang Leung
JSSC Vol38 October 2003