Help me programing an 8-bit latch with reset in verilog

[stuntmaster]

Verilog help plz

hi everyone i've tried to program an 8-bit latch in verilog with reset function
it should work as follow
if g==1 the 8-bit data will be latched and it will appear at the output
if g=0 what ever was latched will appear at the output
if reset=0 all 8-bit data will be zero and it will remain zero until g is logic one again

i' ve tried this code but it doesn't seem to work

hlep me plz



module latch1 (
q,
g,
d,
reset
);

output [7:0] q ;
input g;
input [7:0] d;

input reset ;
reg [7:0] q;
always @(d, g,reset) begin: _latch_logic
if ((g == 1) && (reset==0)) begin
q <= d;
end
else
q<=8'b0;
end

endmodule

 

[Guest]

Re: Verilog help plz

Try this

always @ *
begin

  if (reset)
    q = 8'h00;
  else if (g)
    q = d;

end

 

[stuntmaster]

Verilog help plz

thx for ur help
it worked