Presumed both codes are functionally equivalent (they look like at first sight), then the decision is just a matter of taste or style. Readability would be my personal priority.
In both second examples, you changed concurrent code into sequential. It has no immediate implications in the present case, but literally it's a different kind of behavioral description. You could choose sequential code in VHDL as well, but you didn't for some reason.
what are the goal to convert a code from one language to other one?
Most synthesis tools understand both languages and have no problem with mixed language designs. Modelsim however needs an separate license for it (at extra charge), the free vendor editions don't include it. This can be a trivial but plausible reason to translate some design modules.
Finally, some customers don't like one or the other language. They possibly ask you for their convenience to translate delivered code.
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But, in the always block, there is only a single if-else, so I guess it won't effect much if its concurrent or sequential.
May be that is why you said
it has no immediate implications in the present case
That is the code I want to convert. I cannot change it.
Most synthesis tools understand both languages and have no problem with mixed language designs. Modelsim however needs an separate license for it (at extra charge), the free vendor editions don't include it. This can be a trivial but plausible reason to translate some design modules.
Finally, some customers don't like one or the other language. They possibly ask you for their convenience to translate delivered code