Help me On PLDA EZDMA PCIE? I've problem with interrupt.

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Hi,
I've a sever problem with PLDA EZDMA Core. please help me to rectify this problem.
I'm so confused about it.

recently I have done a project successfully for send and receive data with DMA engines on ML605 board using this core.

Now I'm trying to use it on Virtex5-SX50 pcie board. the project is made and it's seems good but there is a problem with DMAs.

When I continue to run DMAs, after some seconds everything stops.
when I check the PCIE device by PciTree I see that everything about this PCIe device is lost. Device ID and Vendor ID are correct but address of BAR0 or any other thing is changed and the PCIE interface is lost. driver not works and everything fails.
for example reading of registers returns 0xffffffff.

I think this is because of many interrupts that I make in FPGA and cause the driver to crash?
any one can help me? is this state familiar to any body?

 

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As you must have bought the core why don't you get support from PLDA?

 

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Hi,
I think this the problem source is not from plda code. I tested again with step by step help from PLDA and used their Demo application.

PC hangs when I starts read-write DMA together but in a single Write test it has better result(but is not stable and hangs after some minutes).

where should be the source of error?

 

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Re: Help me On PLDA EZDMA PCIE? I've problem with PC Memory Write DMA.

Hi,
I think this the problem source is not from plda code. I tested again with step by step help from PLDA and used their Demo application.

PC hangs when I starts read-write DMA together but in a single Write test it has better result(but is not stable and hangs after some minutes).

where should be the source of error?

searching for answer I reached this page:
http://www.xilinx.com/support/answers/34444.html

it says:

Most downstream ports advertise infinite completion data credits, but when the Endpoint Block Plus core is interfacing with a link partner that is advertising data limited completion credits, it is possible that a transmit direction stall or lockup might occur.

For example, if the link partner advertises initial CPLH credits as 22 and the initial CPLD credits as 128, for an MPS of 128 then:

128 < 22 * 8 * 1
128 < 176

In this example, the equation evaluates to TRUE and the restriction is hit.

I cant understand clearly, please help me to find answer.

My questions is that
1)What is my link partner? Motherbaord or PLDA EZDMA IP Core?
2) How can I find CPLD and CPLH values?