Help me multiple carrier a with input in VHDL for BPSK modulator

[nirav]

Hi,
I want to design a BPSK modulator in VHDL.
My final goal is to do BPSK modulation of two channels, combine them through OVSF code then send it. At receiver side extract sent channels through de-scramblling + de-modulation.

I don't understood why I need to store magnitude of sine wave in Look-up-table.

Till now as a whole thing I have designed UART in VHDL.

The concept regarding modulation in HDL is totally new for me. Main problem I am facing is to multiply a carrier with input (I know regarding different modulation techniques but w.r.t sine wave). If possible please give me some referance/link which can solve my doubt.

Thanks,
Nirav

 

[kib]

bpsk modulator xor

Hi,
I am also looking for a reference design/paper for BPSK modulator implementation in FPGA. If anybody have some link please post it here.
Thanks
kib

 

[vinodkumar]

explain vhdl code for bpsk modulation

Hi
it would be better if u design differential BPSK,if ur problem supports this.b'coz its only to model some basic gates xor or xnor.i.e if ur purpose to modulate the signals.earlier i have modeled CDMA.where i modeled this.


Dont forget to press helped.if u need any more in this i will help u.

 

[lomtik]

the value modulator bpsk

..
I don't understood why I need to store magnitude of sine wave in Look-up-table.
..
Thanks,
Nirav

Hi,

The reason you need to store the magnitude of the sine wave in a look-up-table is because it is one of the easier ways to generate it. So, you'll need to create a table with sine wave values. Each of them will be indexed. Then you'll need a counter to loop through them, each time asking to return a value of a sine wave based on counter index. Once you have the value returned by your new sine wave generator function (your table in other words), you can directly output it to a pin of FPGA. If you probe it with oscilloscope, you'll see the sine wave. The frequency will depend on the counter speed.

Now, if you want to create a BPSK modulator, you'll need to have 180 degree shifted versions of this wave. Since BPSK is similar to BAM, 180 degree shift means just multiplying by -1, or simply outputting the negative value that is returned from your table. So, If you have one bit per symbol as in real BPSK, create an IF statement in VHDL and if your data is +1, output the whole wave period from a table as is. If it is -1, then just output its inverted value!

I saw a website somewhere which had a Perl based VHDL code generator for sinewave lookup table. You can specify a number of sampling points and it will give you the whole table you can shift through.

This should help

Added after 3 minutes:

To optimize the sine wave storage space, you can save just 1/4 of the period and create a little algorithm to increase/decrease the counter and flip the output accordingly depending at which part of T you are at.

For example,
2nd quarter for sin wave will be reducing the counter, so you are outputting values from max to min.
-for 3rd - you are going into negative, so you are increasing your counter, but outputting the negative value.
etc..

 

[sp3_kapil]

psk modulator implementation

I want to design a BPSK modulator in VHDL.
My final goal is to do BPSK modulation of two channels, combine them through OVSF code then send it. At receiver side extract sent channels through de-scramblling + de-modulation.

I don't understood why I need to store magnitude of sine wave in Look-up-table.

Till now as a whole thing I have designed UART in VHDL.