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Help me make an auto counter in Vhdl

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BooM

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hi ,

I am newbie in vhdl and i want help plz.

I have to do an auto counter.
more specific : when I press a button then a display (which i have placed for output ) get starts count 0 to 9. Is it possible to give an example??

I am working on a spartan-3e.

Thank you in advance!
 

nxtech

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Re: HELP in Vhdl

If you have to do a counter for a project then you must have a book on VHDL. There is an example of a counter in that book and if by some exceptionally small chance there is not a counter example you need to throw that book away.

After you locate the counter example in your textbook then all you need to do is place a condition in your process that will activate your counter.

E
 

lordsathish

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Re: HELP in Vhdl

Hope this will help you...but you have to learn vhdl first...thenonly you can write ode that suits you...

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY counter IS
port (clk,re : in std_logic;
q : out std_logic_vector( 3 downto 0););
END ENTITY counter;

ARCHITECTURE ars OF counter IS
signal s_q : std_logic_vector( 3 downto 0) ;
BEGIN
process(clk,s_q)
begin


if rising_edge(clk) then
s_q <=s_q + "0001";
end if;
q<=s_q;

end process;


END ARCHITECTURE ars;
 

BooM

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Re: HELP in Vhdl

hi lordsathish,

thank you for your help!!!
I caught the "(3 down to 0)" :D !
Can you tell me plz where is the different between "if clk=1 and clk'event=1 then..." with "if rising_edge(clk) then.."?

Thank you again!
 

avimit

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Re: HELP in Vhdl

Can you tell me plz where is the different between "if clk=1 and clk'event=1 then..." with "if rising_edge(clk) then.."?
There is absolutely no difference between the two, you may use any of these ae per your taste ;)
Kr,
Avi
http://www.vlsiip.com
 

BooM

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Re: HELP in Vhdl

Thank you avimit !!!!
 

LatDrIvE

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Re: HELP in Vhdl

Have a look on xilinx ISE into the docs directory about "HDL coding techniques"
 

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