In the circuit given, the gain is unity(closed loop).
The open-loop gain would simply be Gm*(RdsM8 || RdsM2). Since it looks like a 40nm process the channel length modulation is quite high and so the gain quite low. If possible try to use longer channel lengths. Also this can't be used as an accurate bufer. The circuit is not balanced(current-mirror load) so the systemic offset will be quite high.
My only question about your reply is that you mention "RDS" but RDS is generally notation for the channel resistance which is very low. Shouldn't it instead be ro, the electronic resistance, which is very high, correct?
My only question about your reply is that you mention "RDS" but RDS is generally notation for the channel resistance which is very low. Shouldn't it instead be ro, the electronic resistance, which is very high, correct?
Rds is just the inverse of Gds(channel length modulation conductance). Ro(output resistance) in this particular case is the parallel combination of the PMOS Rds and NMOS Rds. Draw the small signal equivalent and it will be much more clear.
In most cases Ro is less than Rds because you usually have a drivng transistor and a load. It can be higher if you opt for cascode, gain boosting etc.