Help me implement a digital VHDL limiter

[mwmmboy]

Hi,
I am developing an analog FM demodulator in a FPGA. I am trying to implement a limiter.
Do you have some suggestion? I tried to implement a hysteresis comparator but the problem is the freqeuncy shfting between the sampling frequency and the incoming frequency...


Thanks in advance

Best regards.


MWMM

 

[treqer]

Re: Digital VHDL limiter

there. write

if input > 100 then
output <= 100;
elsif input < -100 then
output <= -100;
else
output <= input ;
end if;

 

[mwmmboy]

Re: Digital VHDL limiter

there. write

if input > 100 then
output <= 100;
elsif input < -100 then
output <= -100;
else
output <= input ;
end if;

Thanks, but if you try this code you will not have an FM wave clipped but it is distorted...What I need is to clip an FM wave coming from an ADC converter. In the else branch if the threshould is too low you due to the noise the amplitude is changeing wrong... in the thresould is higher the wave i distorted.

 

[treqer]

Re: Digital VHDL limiter

I do not know how the digital method. In the analog amplifier-limiter of intermediate frequency converts the input signal is actually a square wave. Thus misses the amplitude information. further by the discriminator circuit is allocated angular modulation component.