help me for CPLD power reduction tech??

[niks]

Im using XCR3064XL CPLD from CoolRunner II family. I would like to know how can i reduce the power consumption in this . one option im having is use constraint COOL_CLK . Any other technic to reduce power consuption.
one other thing i would like to know is, if im not using some flops in cpld then how can i power-off those flops as well as stop clockin the same.
thanks in advance
~niks~

 

[eltonjohn]

Power comsumption in programable devices depends on the activly switching cells or modules .The less of these are swithing at a giving time,.
the less the current drawn is .The higher the frequency of the clock the more often logig will swich and the more current it will use.
Try to acomodate these insight to your design .I remember a design i did years ago and i hat to lower power comsumption .I ended up using pterms in the output enable and only using the outputs when i needed thes .I mean i put the poutputs in high impedance and only enable them quen they needed to be .

 

[falling_stone]

Hi,
You may try to make the design completely asynchronous (without clock at all, and thus consuming power only during external events) or if You have any event indicating external signal You can make it global clock enable (and output enable as EltonJohn mentioned)
Best Regards,
F.S.