leoren_tm
Advanced Member level 1
i have code traffic light but still have a problem on reset and pause..
pls help me in..
Added after 4 minutes:
state machine
pls help me in..
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY trafficlight IS
PORT(
start,pause,reset,clock : in std_logic;
seven_segment : OUT STD_LOGIC_VECTOR(10 downto 0);
led_display : OUT STD_LOGIC_VECTOR(7 downto 0));
END trafficlight;
ARCHITECTURE a OF trafficlight IS
TYPE STATE_TYPE IS (s1, s2, s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
TYPE STATE_TYPE2 IS (p1,p2,p3,p4);
SIGNAL state: STATE_TYPE;
SIGNAL state2: STATE_TYPE2;
signal clock_delay,clock_seconds : std_logic ;
BEGIN
PROCESS (clock)
VARIABLE cnt : INTEGER RANGE 0 TO 4096;
BEGIN
IF (clock'EVENT AND clock = '1') THEN
cnt := cnt + 1;
IF (cnt >= 2048 and cnt < 4096) THEN
clock_delay <= '1' ;
elsif (cnt >=4096) then
cnt := 0 ;
ELSif (cnt <= 2047) then
clock_delay <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clock)
VARIABLE count_to_second : INTEGER RANGE 0 TO 50000000;
BEGIN
IF (clock'EVENT AND clock = '1') THEN
count_to_second := count_to_second + 1;
IF (count_to_second >= 25000000 and count_to_second < 50000000) THEN
clock_seconds <= '1' ;
elsif (count_to_second >=50000000) then
count_to_second := 0 ;
ELSif (count_to_second <= 25000000) then
clock_seconds <= '0';
END IF;
END IF;
END PROCESS;
process (clock_delay,clock_seconds)
begin
if clock_seconds'event and clock_seconds='1' then
case state is
when s1 =>
state <= s2;
led_display <="00100001";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s2 =>
state <= s3;
led_display <="00100001";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s3 =>
state <= s4;
led_display <="00100001";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s4 =>
state <= s5;
led_display <="00100001";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s5 =>
state <= s6;
led_display <="00100001";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s6 =>
state <= s7;
led_display <="00100010";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01000000111";--G
when p2 =>
state2 <=p3;
seven_segment <="00000011011";--O
when p3 =>
state2 <=p4;
seven_segment <="01001001101";--S
when p4 =>
state2 <=p1;
seven_segment <="11100001110";--t
end case;
end if;
when s7 =>
state <= s8;
led_display <="00001100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
when s8=>
state <= s9;
led_display <="00001100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
when s9=>
state <= s10;
led_display <="00001100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
when s10=>
state <= s11;
led_display <="00001100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
when s11=>
state <= s12;
led_display <="00001100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
when s12=>
state <= s1;
led_display <="00010100";
if clock_delay'event and clock_delay='1' then
case state2 is
when p1 =>
state2 <=p2; --abcdefg --
seven_segment <="01001000111";--S
when p2 =>
state2 <=p3;
seven_segment <="11100001011";--t
when p3 =>
state2 <=p4;
seven_segment <="01000001101";--G
when p4 =>
state2 <=p1;
seven_segment <="00000011110";--O
end case;
end if;
end case;
end if;
end process;
END a;
Added after 4 minutes:
state machine