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Help me fix problems with reset and pause in traffic lights coding

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leoren_tm

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i have code traffic light but still have a problem on reset and pause..
pls help me in..
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY trafficlight IS
PORT(
	start,pause,reset,clock : in std_logic;
	seven_segment : OUT STD_LOGIC_VECTOR(10 downto 0);
	led_display : OUT STD_LOGIC_VECTOR(7 downto 0));
END trafficlight;

ARCHITECTURE a OF trafficlight IS
	TYPE STATE_TYPE IS (s1, s2, s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
	TYPE STATE_TYPE2 IS (p1,p2,p3,p4);
	SIGNAL state: STATE_TYPE;
	SIGNAL state2: STATE_TYPE2;
	signal clock_delay,clock_seconds : std_logic ;
	
BEGIN

PROCESS (clock)
VARIABLE cnt : INTEGER RANGE 0 TO 4096;
BEGIN

	IF (clock'EVENT AND clock = '1') THEN
		cnt := cnt + 1;
		IF (cnt >= 2048 and cnt < 4096) THEN
			clock_delay <= '1' ;
		
		elsif (cnt >=4096) then
			cnt := 0 ;
		ELSif (cnt <= 2047)  then
			clock_delay <= '0';	
	END IF;
	END IF;	
END PROCESS;
PROCESS (clock)
VARIABLE count_to_second : INTEGER RANGE 0 TO 50000000;
BEGIN

	IF (clock'EVENT AND clock = '1') THEN
		count_to_second := count_to_second + 1;
		IF (count_to_second >= 25000000 and count_to_second < 50000000) THEN
			clock_seconds <= '1' ;
		
		elsif (count_to_second >=50000000) then
			count_to_second := 0 ;
		ELSif (count_to_second <= 25000000)  then
			clock_seconds <= '0';	
	END IF;
	END IF;	
END PROCESS;
				process (clock_delay,clock_seconds)
					begin
						if clock_seconds'event and clock_seconds='1' then
								case state is
								when s1 =>
								state <= s2;
								led_display <="00100001";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;
								when s2 =>
								state <= s3;
								led_display <="00100001";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;
								when s3 =>
								state <= s4;
								led_display <="00100001";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;
								when s4 =>
								state <= s5;
								led_display <="00100001";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;
								when s5 =>
								state <= s6;
								led_display <="00100001";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;	
								when s6 =>
								state <= s7;
								led_display <="00100010";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01000000111";--G
											when p2 =>
											state2 <=p3;
											seven_segment <="00000011011";--O
											when p3 =>
											state2 <=p4;
											seven_segment <="01001001101";--S
											when p4 =>
											state2 <=p1;
											seven_segment <="11100001110";--t
											end case;
									end if;
								when s7 =>
								state <= s8;
								led_display <="00001100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
								when s8=>
								state <= s9;
								led_display <="00001100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
								when s9=>
								state <= s10;
								led_display <="00001100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
								when s10=>
								state <= s11;
								led_display <="00001100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
								when s11=>
								state <= s12;
								led_display <="00001100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
								when s12=>
								state <= s1;
								led_display <="00010100";
									if clock_delay'event and clock_delay='1' then
											case state2 is
											when p1 =>
											state2 <=p2;    --abcdefg     --
											seven_segment <="01001000111";--S
											when p2 =>
											state2 <=p3;
											seven_segment <="11100001011";--t
											when p3 =>
											state2 <=p4;
											seven_segment <="01000001101";--G
											when p4 =>
											state2 <=p1;
											seven_segment <="00000011110";--O
											end case;
									end if;
							end case;
							end if;
						end process;
		



END a;
Added after 4 minutes:

state machine
 

leoren_tm

Advanced Member level 1
Joined
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Re: TRAFFIC light

i edited some of it..
now i got an error, cant run it..
"state has more than 1 input.."
hir is my code..an if someone has a xilinx spartan3, could you run it?
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY trafficlight_led IS
PORT(
	start,pause,reset,clock : in std_logic;
	seven_segment : OUT STD_LOGIC_VECTOR(10 downto 0);
	led_display : OUT STD_LOGIC_VECTOR(7 downto 0));
END trafficlight_led;

ARCHITECTURE a OF trafficlight_led IS
	TYPE STATE_TYPE IS (s1, s2, s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
	SIGNAL state: STATE_TYPE;
	signal clock_seconds,pause_state,sevensegment,clock_delay : std_logic ;
	TYPE STATE_TYPE2 IS (p1,p2,p3,p4);
	SIGNAL state2: STATE_TYPE2;
	
	
BEGIN
CLOCK_IN_SECOND: PROCESS (clock)
VARIABLE count_to_second : INTEGER RANGE 0 TO 50000000;
BEGIN

	IF (clock'EVENT AND clock = '1') THEN
		count_to_second := count_to_second + 1;
		IF (count_to_second >= 25000000 and count_to_second < 50000000) THEN
			clock_seconds <= '1' ;
		
		elsif (count_to_second >=50000000) then
			count_to_second := 0 ;
		ELSif (count_to_second <= 25000000)  then
			clock_seconds <= '0';	
	END IF;
	END IF;	
END PROCESS CLOCK_IN_SECOND;
MAIN_CONTROL: PROCESS (pause,start,reset)
	begin
		if start'event and start='1' then
			pause_state <='0';
		end if;
		if pause'event and pause='1' then
			pause_state <='1';
		end if;
		if reset'event and reset='1' then
			state <=s1;
			pause_state <='0';
		end if;
		
end process MAIN_CONTROL;
			LED_DISPLAY_TRAFFIC: process (clock_seconds)
				begin
				if start'event and start='1' then
					if clock_seconds'event and clock_seconds='1' then
							case state is
							when s1 => 	if pause_state='1' then
									state<=s1;
									elsif pause_state='0' then
									state <= s2;
									end if;
							led_display <="00100001";
							sevensegment <='0';--GOSt								
							when s2 =>	if pause_state='1' then
									state<=s2;
									elsif pause_state='0' then
									state <= s3;
									end if;		
							sevensegment <='0';--GOSt
							led_display <="00100001";								
							when s3 =>	if pause_state='1' then
									state<=s3;
									elsif pause_state='0' then
									state <= s4;
									end if;						
							sevensegment <='0';--GOSt
							led_display <="00100001";								
							when s4 =>	if pause_state='1' then
									state<=s4;
									elsif pause_state='0' then
									state <= s5;
									end if;						
							led_display <="00100001";
							sevensegment <='0';--GOSt								
							when s5 =>	if pause_state='1' then
									state<=s5;
									elsif pause_state='0' then
									state <= s6;
									end if;						
							led_display <="00100001";
							sevensegment <='0';--GOSt								
							when s6 =>	if pause_state='1' then
									state<=s6;
									elsif pause_state='0' then
									state <= s7;
									end if;					
							led_display <="00100010";
							sevensegment <='0';--GOSt								
							when s7 =>	if pause_state='1' then
									state<=s7;
									elsif pause_state='0' then
									state <= s8;
									end if;						
							led_display <="00001100";
							sevensegment <='1';--StGO								
							when s8=>	if pause_state='1' then
									state<=s8;
									elsif pause_state='0' then
									state <= s9;
									end if;						
							led_display <="00001100";
							sevensegment <='1';--StGO								
							when s9=>	if pause_state='1' then
									state<=s9;
									elsif pause_state='0' then
									state <= s10;
									end if;							
							led_display <="00001100";
							sevensegment <='1';--StGO								
							when s10=>	if pause_state='1' then
									state<=s10;
									elsif pause_state='0' then
									state <= s11;
									end if;					
							led_display <="00001100";
							sevensegment <='1';--StGO
							when s11=>	if pause_state='1' then
									state<=s11;
									elsif pause_state='0' then
									state <= s12;
									end if;							
							led_display <="00001100";
							sevensegment <='1';--StGO								
							when s12=>	if pause_state='1' then
									state<=s12;
									elsif pause_state='0' then
									state <= s1;
									end if;							
							led_display <="00010100";
							sevensegment <='1';--StGO
								
						end case;
						end if;
					end if;
				end process LED_DISPLAY_TRAFFIC;
CLOCK_DELAY_FOR_7SEGMENT: PROCESS (clock)
VARIABLE count : INTEGER RANGE 0 TO 4096;
BEGIN

	IF (clock'EVENT AND clock = '1') THEN
		count := count + 1;
		IF (count >= 2048 and count < 4096) THEN
			clock_delay <= '1' ;
		
		elsif (count >=4096) then
			count := 0 ;
		ELSif (count <= 2047)  then
			clock_delay <= '0';	
	END IF;
	END IF;	
END PROCESS CLOCK_DELAY_FOR_7SEGMENT;
SEVEN_SEGMENT_DISPLAY: process(clock_delay)
	begin
		if clock_delay'event and clock_delay='1' then
			if sevensegment='0' then
				case state2 is
				when p1 =>
				state2 <=p2;    --abcdefg     --
				seven_segment <="01000000111";--G											
				when p2 =>
				state2 <=p3;
				seven_segment <="00000011011";--O
				when p3 =>
				state2 <=p4;
				seven_segment <="01001001101";--S
				when p4 =>
				state2 <=p1;
				seven_segment <="11100001110";--t
				end case;
			elsif sevensegment='1' then
				case state2 is
				when p1 =>
				state2 <=p2;    --abcdefg     --
				seven_segment <="01001000111";--S
				when p2 =>
				state2 <=p3;
				seven_segment <="11100001011";--t
				when p3 =>
				state2 <=p4;
				seven_segment <="01000001101";--G
				when p4 =>
				state2 <=p1;
				seven_segment <="00000011110";--O
				end case;
			end if;
		end if;
end process SEVEN_SEGMENT_DISPLAY;
		



END a;
for testbecnh
Code:
library ieee;
use ieee.std_logic_1164.all;

entity TestBench is
end TestBench;

architecture TB of TestBench is

component trafficlight_led
PORT(
	start,pause,reset,clock : in std_logic;
	seven_segment : OUT STD_LOGIC_VECTOR(10 downto 0);
	led_display : OUT STD_LOGIC_VECTOR(7 downto 0));
END component;

signal start,pause,reset,clock : std_logic;
signal seven_segment : STD_LOGIC_VECTOR(10 downto 0);
signal led_display : STD_LOGIC_VECTOR(7 downto 0);
begin
	
	DUT : trafficlight_led port map (start=>start, pause=>pause, reset=>reset,clock=>clock,seven_segment=>seven_segment,led_display=>led_display);
	process
		begin
		clock <='0','1' after 20 ns;
		wait for 40 ns;
		end process;
		start <= '0', '1' after 1000000 ns, '0' after 1000040 ns,'1' after 5000000 ns;
		pause <= '0', '1' after 2000000 ns, '0' after 2000040 ns;
		reset <= '0', '1' after 9 ms;
		
end TB;
 

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