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Spot the VHDL error...
Can anybody tell me what is wrong with the attached piece of VHDL please?. Xilinx ISE 7.1 is telling me it expects to see see IF rather than PROCESS near the end. I have looked at it too long if you know what I mean.
TIA
Git
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( enb : in std_logic;
dir : in std_logic;
clk : in std_logic;
rst : in std_logic;
op : out std_logic_vector(1 downto 0));
end counter;
architecture Behavioral of counter is
signal t_op : std_logic_vector(1 downto 0);
signal t_5 : std_logic_vector(2 downto 0);
begin
op <= t_op;
process(clk, rst, enb, dir)
begin
if rst='1' then
t_op <= "00";
t_5 <= "000";
else if clk = '1' and clk'event then
if enb = '1' then
if dir = '1' then -- Count UP
if t_5 = "100" then
t_5 <= "000";
t_op <= t_op + '1'; -- Carry
else
t_5 <= t_5 + '1';
end if;
else
if t_5 = "000" then
t_5 <= "100";
t_op <= t_op - '1'; -- Borrow
else
t_5 <= t_5 - '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
Can anybody tell me what is wrong with the attached piece of VHDL please?. Xilinx ISE 7.1 is telling me it expects to see see IF rather than PROCESS near the end. I have looked at it too long if you know what I mean.
TIA
Git
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( enb : in std_logic;
dir : in std_logic;
clk : in std_logic;
rst : in std_logic;
op : out std_logic_vector(1 downto 0));
end counter;
architecture Behavioral of counter is
signal t_op : std_logic_vector(1 downto 0);
signal t_5 : std_logic_vector(2 downto 0);
begin
op <= t_op;
process(clk, rst, enb, dir)
begin
if rst='1' then
t_op <= "00";
t_5 <= "000";
else if clk = '1' and clk'event then
if enb = '1' then
if dir = '1' then -- Count UP
if t_5 = "100" then
t_5 <= "000";
t_op <= t_op + '1'; -- Carry
else
t_5 <= t_5 + '1';
end if;
else
if t_5 = "000" then
t_5 <= "100";
t_op <= t_op - '1'; -- Borrow
else
t_5 <= t_5 - '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;