Help me find the error in this VHDL code

[Git]

Spot the VHDL error...

Can anybody tell me what is wrong with the attached piece of VHDL please?. Xilinx ISE 7.1 is telling me it expects to see see IF rather than PROCESS near the end. I have looked at it too long if you know what I mean.

TIA

Git

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( enb : in std_logic;
dir : in std_logic;
clk : in std_logic;
rst : in std_logic;
op : out std_logic_vector(1 downto 0));
end counter;

architecture Behavioral of counter is
signal t_op : std_logic_vector(1 downto 0);
signal t_5 : std_logic_vector(2 downto 0);
begin
op <= t_op;
process(clk, rst, enb, dir)
begin
if rst='1' then
t_op <= "00";
t_5 <= "000";
else if clk = '1' and clk'event then
if enb = '1' then
if dir = '1' then -- Count UP
if t_5 = "100" then
t_5 <= "000";
t_op <= t_op + '1'; -- Carry
else
t_5 <= t_5 + '1';
end if;
else
if t_5 = "000" then
t_5 <= "100";
t_op <= t_op - '1'; -- Borrow
else
t_5 <= t_5 - '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;

 

[lucbra]

Re: Spot the VHDL error...

Have you wrote the code with indent's original.

I guess the problem sits in the else if clk = '1' and clk'event then

change to elsif clk'event and clk = '1' then

 

[Git]

Re: Spot the VHDL error...

Doh!. I *always* do that!. Thanks very much.

Yes, source was originally indented OK but the tabs got removed when posting. I think there's a posting tag I should have used.

Git

 

[nand_gates]

Re: Spot the VHDL error...

Here is the corrected code one "end if " was missing ...
Hope the code works now!

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
  port ( enb : in  std_logic;
         dir : in  std_logic;
         clk : in  std_logic;
         rst : in  std_logic;
         op  : out std_logic_vector(1 downto 0));
end counter;

architecture Behavioral of counter is
  signal t_op : std_logic_vector(1 downto 0);
  signal t_5  : std_logic_vector(2 downto 0);
begin
  op                  <= t_op;
  process(clk, rst, enb, dir)
  begin
    if rst = '1' then
      t_op            <= "00";
      t_5             <= "000";
    else
      if clk = '1' and clk'event then
        if enb = '1' then
          if dir = '1' then          -- Count UP
            if t_5 = "100" then
              t_5  <= "000";
              t_op <= t_op + '1';    -- Carry
            else
              t_5  <= t_5 + '1';
            end if;
          else
            if t_5 = "000" then
              t_5  <= "100";
              t_op <= t_op - '1';    -- Borrow
            else
              t_5  <= t_5 - '1';
            end if;
          end if;
        end if;
      end if;
    end if;
  end process;
end Behavioral;

 

[DSa]

Spot the VHDL error...

why don't you like rising_edge(clk)?

 

[dcreddy1980]

Re: Spot the VHDL error...

yes, as pointed out by nand_gates...one "end if" statement is missing.