library ieee;
use ieee.std_logic_1164.all;
entity crc5 is
port( clk: in std_logic;
rst: in std_logic;
stuffed_data: in std_logic;
out_crc5: out std_logic_vector(4 downto 0));
end crc5;
architecture crc5 of crc5 is
signal crc5_state : std_logic_vector(4 downto 0);
begin
process
variable shift_register : std_logic_vector(4 downto 0);
begin
WAIT UNTIL clk'EVENT AND clk = '1';
crc5_state <= shift_register;
out_crc5 <= NOT crc5_state;
if rst = '1' then
shift_register := "11111";
out_crc5 <= "11111";
ELSE
crc5_state(4) <= crc5_state(3);
crc5_state(3) <= crc5_state(2);
crc5_state(2) <= crc5_state(1)xor stuffed_data xor crc5_state(4);
crc5_state(1) <= crc5_state(0);
crc5_state(0) <= stuffed_data xor crc5_state(4);
shift_register := crc5_state;
end if;
end process;
end crc5;