Help me do a layout of a mim capacitor in TSMC process

[cmos_dude]

Hi All
I need to do a layout for a mim capacitor in a TSMC process.
Can anybody help me out with it.
Please be specific about all the marker layers required for the layout.

Also if possible, please provide with a snapshot of the layout of a mim cap. I have no idea how it looks as I have never done it before.

Thanks for your help

--cmos_dude

 

[protonixs]

Re: mim capacitor

layers are:
M5
MV4
M4
MCT_dg
DUM_MCT_dg
MCTDMY_dg

 

[fixrouter4400]

Re: mim capacitor

These are the layers used to layout mimcaps.

1. CTMDUMMY - drw
2. CTM4 - drw
3. METAL4 - drw (bottom metal)
4. VIA45 - drw
5. METAL5 - drw (top metal)
6. METAL4 - pin[/img]

 

[cmos_dude]

mim capacitor

Hi
Thanks for your help, it will prove to be of real help.

Although I still have some more queries.
In my calibre deck, I see a CTM and a CBM layer for identifying the capacitor, but you have not mentioned the CBM layer. Am I missing something ???

--cmos_dude