Hi All
I need to do a layout for a mim capacitor in a TSMC process.
Can anybody help me out with it.
Please be specific about all the marker layers required for the layout.
Also if possible, please provide with a snapshot of the layout of a mim cap. I have no idea how it looks as I have never done it before.
Hi
Thanks for your help, it will prove to be of real help.
Although I still have some more queries.
In my calibre deck, I see a CTM and a CBM layer for identifying the capacitor, but you have not mentioned the CBM layer. Am I missing something ???