Help me design this kind of DPLL

[xdlongzi]

Help , carrier track!

In my design(DS/BPSK), after digital down convert(multiplied by sine and cosine, so I and Q can be gotten) ,PN acquire and FLL(frequency locked loop, θ=atan(I/Q), θ(n+1)-θ=Δω*Ts, so Δω gotten ), the residual frequency offset was about 70Hz, in order to remove this , a DPLL is adopted .
Can anybody tell me how to design this DPLL?

thanks!

 

[dora]

Re: Help , carrier track!

Hi

There are lot of books for PLLs and Digital Communications in the edaboard ... just use the search engine and will find plenty of literature
on the topic.

dora

 

[xdlongzi]

Re: Help , carrier track!

thank u!
i have simulated it in systemview.
but there is difficult for me to implement in matlab (no simulink).

 

[hmahdi12]

Help , carrier track!

what problem do u encountered?

 

[ljkong]

Re: Help , carrier track!

maybe it is difficult for you to implement using matlab.
using simulink is so easy.
why not use it?