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Help me!(Design of 10 bit DAC)

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liccAMS

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hello friends

we now should design of 10 bit DAC with 2.5v process.Power and noise are the most important things we need conside.INL, DNL under 1 LSB
If we use the R-2R structure,the mismatch and power may limit us to attach the requirement.
Can you give me some advices about what architecture should I use.


hoping your replay
thanks in advace
 

sunking

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it depond on your speed, power.
many architecture you can use.
voltage weighting, current weighting, charge weighting, single slope, dural slope and so on
 

paulux

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What is the speed/application of DAC?

Hi sunking,

Given the requirement of 10bit DAC with less than 1LSB in INL & DNL,
what are the factors determining the architecture of DAC?
could you recommend some references/papers for the techniques you described?
 

zkkbmy

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I think the book-CMOS DATA CONVERTERS FOR COMMUNICATIONS can help you! you download this book in edaboard. hope it can help you.
 

liccAMS

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hi paulux:

the speed is about 1MSPS
used for AFC, APC of analog base band

can anyone help me getting some related documents?thnx!
 

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