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Aync fifo depth calculation is very critical.
Depending on your clock difference between two domains you have to calculate the "slip" and then decide the frame size you need to store.
If totally async (read clk 5Mhz and write clk 7 Mhz), then u need to be a little careful. You need to chk at what time you need the data on the read side and stop writing until you generate empty flag.
If you will go for in-built async FIFOs within the FPGA then it will be better than looking out to design. Just use megawizard for Altera devices (I dn't hving idea about xilinx) which you can find in Quartus software.
You can built your FIFO as per your requirement. Just open megawizard and choose a FIFO.