Help me design an asynchronous FIFO

[Harinadhan]

i want to design an asynchronous FIFO.........
please help me..

 

[Srinivas Akula]

Re: asynchronous FIFO

Hi Harinadhan

Aync fifo depth calculation is very critical.
Depending on your clock difference between two domains you have to calculate the "slip" and then decide the frame size you need to store.

If totally async (read clk 5Mhz and write clk 7 Mhz), then u need to be a little careful. You need to chk at what time you need the data on the read side and stop writing until you generate empty flag.

Regards,
Srinivas

 

[vantage]

Re: asynchronous FIFO

Here you go :

A simple explanation on Fifo from my side !

And Snug paper :
www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf

 

[Iouri]

asynchronous FIFO

why not to use FIFO generate by your FPGA software???

 

[sachingorkhe]

asynchronous FIFO

If you will go for in-built async FIFOs within the FPGA then it will be better than looking out to design. Just use megawizard for Altera devices (I dn't hving idea about xilinx) which you can find in Quartus software.

You can built your FIFO as per your requirement. Just open megawizard and choose a FIFO.