Help me design a state machine to divide the clock by 3/2

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santumevce1412

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Design a state machine to divide the clock by 3/2.

I/p frequency - 50MHz
o/p requency - 33.3MHz
 

frequency divider

If your output frequency is fixed at 33.3 MHz then you may simply use the oscillator working at that freq.
 

Re: frequency divider

you can design an 2-bit counter named "cnt[1:0]", return "00" when count to "10", negedge of clk;
then you can generate an 2/3 clk by this statement:
assign clk_out=clk&~cnt[1];
 

Re: frequency divider

what about the duty cycle??
 

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