Help me design a state machine to divide the clock by 3/2

[santumevce1412]

Design a state machine to divide the clock by 3/2.

I/p frequency - 50MHz
o/p requency - 33.3MHz

 

[nisarg001]

frequency divider

If your output frequency is fixed at 33.3 MHz then you may simply use the oscillator working at that freq.

 

[wudanyu]

Re: frequency divider

you can design an 2-bit counter named "cnt[1:0]", return "00" when count to "10", negedge of clk;
then you can generate an 2/3 clk by this statement:
assign clk_out=clk&~cnt[1];

 

[ranjithp]

Re: frequency divider

what about the duty cycle??

 

[ramana459]

Re: frequency divider

use this url
https://asic-world.com/examples/verilog/divide_by_45.html#Divide_By_4.5_Counter
by using this code you modify your code into according your interest